9. Pipelined Cell🔗

The fully synchronous cell pays three clocks per instruction because it never overlaps its phases. This chapter overlaps them for throughput and proves the result still commits the sequential trace. The overlap is deliberately narrow: only instruction fetch runs ahead. That is exactly the overlap this instruction set makes safe.

The reasoning turns on which hazards exist. There is no data hazard from register, accumulator, or pointer dependencies, because each instruction still executes against the fully committed architectural state — commits stay one-per-cycle and in order, so every operand read sees all prior writebacks. The instruction memory is read-only while the cell runs, so a prefetched instruction never depends on a writeback either. The one hazard is control: the prefetch predicts the fall-through address pc + 1, and a taken branch or a halt makes that prediction wrong. A wrong prefetch is caught and squashed, costing a single bubble.

The pipeline state adds a fetch latch to the architectural state: a validity bit, the memory index the latched instruction was fetched from, and the instruction itself. The invariant is that a valid latch holds the instruction at its recorded index.

Every clock keeps the fetch-latch invariant: whatever address the latch records, it holds that instruction. Both the hit and miss branches load the latch from the instruction memory at the index they record, and neither writes the instruction memory.

A hit commits exactly what the combinational cell commits in one cycle, so it refines the ISA step for that instruction. The prefetch is validated by the hit condition itself: the latched index equals the wanted index, so by the invariant the latched instruction is the right one.

A miss changes nothing architecturally; it only reloads the latch with the wanted instruction. So a miss is a stutter step, and the state it produces is hit-ready: valid, with the recorded index equal to the wanted index and the invariant restored. The bubble after a mispredict therefore lasts exactly one cycle.

The two combine into the throughput statement: a mispredict bubble followed by its refetch commits exactly one sequential step. Any taken branch costs one lost cycle and no correctness; straight-line code commits one instruction per cycle.